Opening for Verification Engineer(3-10yrs)

2 - 7 Years

Job Description

Job Overview:
Candidate will be responsible for running the implementation flows like PLDRC(Spyglass - Pre Layout Design Rule Checks), CDC(0-in CDC Clock Domain Crossing) and Low Power flows( CLP, Unified Power Flow), Sanity simulations runs and release flows to SoC.

Skills / Experience:
3-10 years of experience in ASIC development
Expertise in Low power flows for CLP, UPF ( Cadence low power, Unified power format)
Experience in formal verification with Cadence LEC
Experience in Spyglass Lint/CDC checks and waiver creation
Experience in RTL HDL languages Verilog/VHDL Understanding of RTL to GDS flow
Expertise in Perl, TCL language is a plus Previous experience in QC flow is a plus

Salary: INR 5,00,000 - 15,00,000 P.A.

Employment Type:Permanent Job, Full Time


Desired Candidate Profile

Please refer to the Job description above


Doctorate:Doctorate Not Required

Company Profile

Zilogic Systems Pvt Ltd

Zilogic Systems Pvt Ltd
View Contact Details+

Contact Company:Zilogic Systems Pvt Ltd